Single chip data processors often comprise an arithmetic logic unit (ALU) which is coupled via a data bus to a memory. The memory is typically an array memory having both a column decoder and a row decoder. The column and row decoders function generally by decoding one or more input signals and driving an output signal to the memory array which is primarily a capacitive load. Within most decoder/driver circuits is a dynamic node which is the output of a decode portion and biases a driver output stage. Due to undesired capacitive coupling between the dynamic node and the driver output stage, the voltage potential of the dynamic node is degraded and reduced in value. As a result of the reduced voltage which biases the driver output stage, the output voltage of the driver does not immediately transition resulting in slow data access times within the memory. Because of processing and layout variations, the data access times within the memory may also vary significantly. Others have compensated for the stated circuit condition by using a charge pump to selectively boost the voltage at the dynamic node when needed. An example of such a circuit is taught by Harvey Stiegler in U.S. Pat. No. 4,692,638. The known techniques which compensate for parasitic capacitances causing slow data access times have involved the addition of a significant amount of circuitry and layout considerations.